The present invention relates to a method for fabricating a memory cell arrangement with a folded bit line arrangement, and a corresponding memory cell arrangement with a folded bit line arrangement.
German patent No. 199 28 781 C1 discloses a method for fabricating a memory cell arrangement. This known method involves forming a plurality of active regions in a semiconductor substrate, which are surrounded on all sides by isolation trenches which run perpendicular to one another along a first and second direction. Parallel buried word lines are subsequently formed in each case two adjacent isolation trenches along a first direction, which buried word lines run through a respective active region and are insulated from a channel region in the semiconductor substrate by a gate dielectric layer. A respective source region is formed between the two word lines, and a respective first and second drain region is formed between in each case one of the two word lines and an adjacent isolation trench in each active zone. This is followed by forming a plurality of parallel bit lines along the second direction at the surface of the semiconductor substrate, a bit line in each case running through an associated active region and making contact with the relevant source zone of the associated active region. Finally, a plurality of storage capacitors are formed, in each case a first and a second storage capacitor being connected to an associated drain zone in a respective active region.
Further memory cell arrangements are known, for example, from U.S. Pat. Nos. 6,545,904, 5,502,320, 6,063,669, 6,396,096 B1 and from published European application for patent No. 1 003 219 A2.
Although applicable in principle to any integrated circuits, the present invention and the problem area on which it is based are explained with regard to DRAM memory devices using silicon technology.
Memory cells of a DRAM memory device usually have a storage capacitor for storing electrical charge according to an information state and a selection transistor connected to the storage capacitor. Memory cells of this type are arranged in the surface of a semiconductor substrate and can be driven by means of word and bit lines. The region in the semiconductor substrate in which the selection transistor is formed is generally referred to as the active region. In modern DRAM memory devices, the storage capacitor is usually formed as a trench capacitor or stacked capacitor.
The folded bit line concept is generally understood to mean memory cell arrangements in which every second crossover point between a specific word line and a respective bit line has a memory cell. It is thus possible to route a bit line and an adjacent reference bit line to a sense amplifier and to ensure low-noise operation.